FAQ
For questions not answered in this FAQ or if you require additional support using SimWB, please contact us at support@ccur.com.
Contents
- 1 General Questions
- 2 Using SimWB
- 2.1 SimWB test and sessions
- 2.2 SimWB MLToolkit
- 2.2.1 How does SimWB fit into Model Based Design
- 2.2.2 What is the SimWB Toolkit for MATLAB?
- 2.2.3 How do I create an RTDB from a Simulink model?
- 2.2.4 How are subsystem inports and outports handled during SimWB compliant code generation from the MLToolkit?
- 2.2.5 What is the difference between the configuration RTDB and the shared memory RTDB
- 2.3 SimWB Models
- 2.4 SimWB I/O
- 2.5 SimWB Real-Time Host Files
- 2.6 SimWB HMI
- 3 Troubleshooting
General Questions
What are the system requirements for SimWB?
Please see Installation Prerequisites.
Is there a 64 bit version of SimWB?
Yes, there is a 64 bit version of SimWB which can be installed on the 64 bit RedHawk Operating System.
Does SimWB support 32 and 64 bit MATLAB on Windows and Linux?
Yes, SimWB Toolkit for MATLAB supports both 32 and 64 bit MATLAB (R2008b and later) on Windows as well as Linux. SimWB has a small MATLAB/Simulink footprint so SimWB is easily made compatible with the latest version of MATLAB/Simulink offered by the MathWorks. For MATLAB (R2008a and earlier), please use the Legacy SimWB - MATLAB interface.
What is a Hexadecimal Floating Point Literal
A string literal of the form 0x1.8p1 in SimWB is a Hexadecimalfloatingpointliteral of a double. This notation is used in the Test->InitialCondition files so that the "exact" binary representation of the floating point number can be transmitted over the network in ASCII format.
Hexadecimalfloatingpointliterals are of the form 0x1.8p1 which is used to represent the value 3.
The following extract from [1] which describes the lexical structure of the the HexadecimalFloatingPointLiteral.
HexadecimalFloatingPointLiteral:
HexSignificand BinaryExponent FloatTypeSuffixopt
HexSignificand:
HexNumeral HexNumeral . 0x HexDigitsopt . HexDigits 0X HexDigitsopt . HexDigits
BinaryExponent:
BinaryExponentIndicator SignedInteger
BinaryExponentIndicator:one of
p P
Use the C function strtod to convert a HexadecimalFloatingPointLiteral to a floating point number. Please see the strtod man page for additional information.
Using SimWB
SimWB test and sessions
What is a SimWB test?
A SimWB test is a collection of SimWB resources pulled together to make a runnable configuration.
It is defined with the following resources:
- A RTDB
- The RTDB will define which I/O tasks are run as part of the test run. The set of I/O tasks to run is determined from the RTDB I/O mappings. I.e if a input RTDB item is mapped to a AI64SS channel, an instance of a ai64ss I/O task will be started.
- A test script (optional)
- One or more user models, Simulink models, Third Party (SIMPACK, FMU) models (optional)
- A RTDB
What is a SimWB test session?
A test session is a specific runnable instance of a SimWB test. SimWB sessions always belong to a specific test.
A test session can be pre created by the user and then run repeatedly. Run time configuration parameters can be specified independently for each session.
Those parameters are:
- The scheduling method to use to dispatch the simulation loop:
- Default FBS (RCIM) scheduler.
- Software O/S timer.
- Red line scheduler.
- The set of RTDB and Simulink model parameters initial condition.
- The maximum number of overruns to tolerate during the session run.
- The maximum amount of time alloted to process asynchronous RTDB updates from asynchronous I/O tasks.
- Whether the data logger will be run during the session.
- The scheduling method to use to dispatch the simulation loop:
The session will also retain the data logging files corresponding to the RTDB items values that were logged during the run. Be aware that running the session multiple times will overwrite the data that was recorded during a previous run of the session.
A session can also be auto created at startup with default session parameters specified in the GUI interface.
How do I create test in SimWB?
You create a test via the SimWB control center. In order to create a test, you just specify the RTDB, the optional test scripts and model(s) that are part of the test.
How do I create a test session in SimWB?
Under the SimWB control Center, select the test for which you want to create a test session. Define all the session specific parameters such as scheduler, initial conditions set, data logging,etc, the session name.
A session can also be automatically be created at test startup by selecting auto-create in the session run/playback tab.
How do I log data during a test/session run?
Simply enable data logging when creating the SimWB test session or when starting the test if you use the session auto create mode. The items defined in the RTDB can be marked individually for data logging. The period at which the specific data item is logged can also be specified. The period is specified in milliseconds up to a minimum value corresponding to the frame rate at which the test is run. Additinally, data logging can also be specified in the initial conditions panel in the SimConfig GUI. Data logging of Simlink parameters can be enabled in this panels.
How do I playback a test in SimWB?
A session that was run with data logging enabled can always be played back.
Select the session you want to playback, select the playback mode and run the session.
SimWB MLToolkit
How does SimWB fit into Model Based Design
Model-Based Design is a process that enables faster, more cost-effective development of dynamic systems, including control systems, signal processing, and communications systems. In Model-Based Design, a system model is at the center of the development process, from requirements development, through design, implementation, and testing. The model is an executable specification that is continually refined throughout the development process. After model development, simulation shows whether the model works correctly.
When software and hardware implementation requirements are included, such as fixed-point and timing behavior, you can automatically generate code for embedded deployment and create test benches for system verification, saving time and avoiding the introduction of manually coded errors.
Model-Based Design allows you to improve efficiency by:
- Using a common design environment across project teams
- Linking designs directly to requirements
- Integrating testing with design to continuously identify and correct errors
- Refining algorithms through multidomain simulation
- Automatically generating embedded software code
- Developing and reusing test suites
- Automatically generating documentation
- Reusing designs to deploy systems across multiple processors and hardware targets
The MathWorks is a huge proponent of Model-Based Design and MATLAB and Simulink based tools facilitate in Model-Based Design process. The MLToolkit enables Simulink users to generate code from the models and execute and test the model execution in real-time. SIMulation Workbench is typically used in rapid prototyping, hardware-in-loop testing, and integration testing phases of Model-Based Design.
For additional details please see SIMulation Workbench Toolkit.
What is the SimWB Toolkit for MATLAB?
Please see SIMulation Workbench Toolkit.
How do I create an RTDB from a Simulink model?
Please see SIMulation_Workbench_Toolkit#RTDB_Creator_Tab
How are subsystem inports and outports handled during SimWB compliant code generation from the MLToolkit?
Inports and Outports are different from other Sources and Sinks in Simulink because they behave differently inside and outside of Simulink subsystems. Subsystem inports and inports have to be connected to other blocks in the subsystem one level higher until we reach the root level (bdroot) of the model. At the root level, inports and outports are indicative of signals external to the Simulink model (i.e they come from the outside world). During SimWB compliant code generation the user can choose the following options:
- Map using block names
- Map "SW" prefixed blocks
If the user chooses the first option i.e. Map using block names, inports and outports are picked up only from the root level(bdroot) to be replaced by RTDB variables in the SimWB compliant generated code. All inports and outports within subsystems are ignored and will not be mapped to RTDB variables. If the user chooses the second option i.e. Map "SW" prefixed blocks, inports and outports with the SW prefix are picked up irrespective of which subsystem they are in within the model. For example, lets consider the model shown here.
The SW prefixed inport "SWin1" is picked and replaced by a RTDB variable during SimWB compliant code generation since we are telling RTW that the "SWin1" port data is essentially going to come from an external source. The RTW engine sees this during code generation and infers that the Sine Wave source block is no longer connected to the "SWin1" port for code generation purposes and so the Sine Wave block is optimized out of the generated code. During code generation, you will see a warning which is expected.
Warning: Unconnected output line found on 'testinports/Sine Wave' (output port: 1)
The following is a snippet of the generated code and we can see that the inport "SWin1" is now mapped to a RTDB variable "in1" which is a part of the the cvtTable structure. There is no mention of the "Sine Wave" block as it has been optimized out during the code generation process.
/* Model output function */ static void testinports_output(int_T tid) { /* local block i/o variables */ real_T rtb_SWin1; /* M-S-Function: '<S1>/SWin1' */ /* M-S-Function Block: <S1>/SWin1 */ rtb_SWin1 = cvtTable.in1 ; /* Gain: '<S1>/Gain' */ testinports_B.Gain = testinports_P.Gain_Gain * rtb_SWin1; /* M-S-Function: '<Root>/SWScope' */ /* M-S-Function Block: <Root>/SWScope */ cvtTable.Scope = testinports_B.Gain; /* tid is required for a uniform function interface. * Argument tid is not used in the function. */ UNUSED_PARAMETER(tid); }
The shared memory RTDB is the RTDB which is loaded by a test loaded in memory on the real-time host. When a test is started, the test loads a configuration RTDB into the shared memory RTDB space and then works on the RTDB in shared memory. If I just re-start the real-time host and perform a rtobj.getSharedMemRTDBName, it returns empty since no test is loaded into memory. If I run a test (which will load the test into memory), the same query returns the RTDB name. Even if I stop the test (it is still loaded into memory), the query will return the same RTDB name. If the test is stopped, I can still get the list of variables using the rtobj.getSharedMemRTDBVarList call but getting and setting the item values makes sense only when a test is running.
The configuration RTDB is loaded into a different memory section of the real-time host and this will be unique for each socket connection to the real-time host. For example, say I create the rtobj object to my real-time host ‘redhawk1’ from MATLAB 9a and I create another rtobj object to the same real-time host ‘redhawk1’ from MATLAB 10a, now I have two unique connections to the same real-time host and I can load and work on two different configuration RTDB’s via the two different sockets. Though both the sockets will be accessing the same shared memory RTDB the configuration RTDB’s may be different. Even in the same version of MATLAB, the SimWB Toolkit GUI and the rtobj API use different sockets to connect to the real-time host. Add to this the SIMulation Workbench Control Center (Java GUI) which has its own socket there may be 3 different configuration RTDBs or 3 different copies of the same RTDB.
SimWB Models
Simulation Frame Rate/Fixed Step
In this context , we use frame rate and fixed step (Simulink™ semantics) in the same sense.
Models included as part of a SimWB test are run by default at the same as the main simulation rate during the model sub-cycle. This means that the fixed step used for calculations in the time domain - Integrator, etc. - is by default the same as the main simulation rate.
SimWB I/O
Is there a list of I/O boards supported by SimWB ?
Please see Wide selection of COTS I/O boards.
Synchronous versus Asynchronous I/O in SimWB ?
- Synchronous I/O
- Describes the I/O that takes place inside the simulation loop. The board must generate inputs or accepts outputs at the speed of the simulation. In synchronous I/O the simulation loop drives the I/O and the associated hardware devices and O/S drivers must run deterministically so as not to cause overrun in the simulation loop and leave enough idle time for the user model to run inside the loop.
- In synchronous I/O, inputs are generated at the beginning of the cycle providing for the user models which run next. The models then generate outputs that are processes by the output I/O tasks during the output sub-cycle at the end of the simulation loop.
- Examples of synchronous I/O devices are:
- Analog/digital input/outputs
- Synchro/Resolver
- Relay boards
- Asynchronous I/O
- When a device cannot run at the speed of the simulation loop. It must be processed asynchronously outside of the loop. Asynchronous I/O tasks can receive inputs at any time during the simulation loop on a schedule determined by the device itself. The asynchronous I/O tasks never write to the RTDB directly but update it during the input sub-cycle via a dedicated FIFO and SimWB scheduler sub-process.
- Examples of asynchronous I/O devices are:
- ARINC 429
- AFDX
- Serial ports
- 1553
How do I add support for my own hardware board in SimWB ?
Each individual I/O board supported in SimWB is associated with its own I/O task. An I/O task is a process that handles the inputs / outputs from / to the board and writes / reads them to the Real-time DataBase (RTDB).
SimWB provides a mechanism for the user to write their own I/O tasks and still have them run synchronously as part of the simulation loop or asynchronously when the device / I/O board is asynchronous.
Concurrent will provide you with a complete set of synchronous / asynchronous examples upon request. Please, email support@ccur.com to request the sample code.
SimWB Real-Time Host Files
The default installation directory on the real-time host is /usr/local/ccursim/. SimWB user resources are created/installed under the /usr/local/ccursim/projects/ folder.
RTDB
- One separate folder per RTDB. The folder contains all the files that make up the specific RTDB.
RTW
- Real Time Workshop™ executables models. One folder per executable. The folder name is the name of the executable.
RTW.Sources
- Contains the sources of the Simulink™ models. One folder per model. The sources are created via the SimWB MLToolkit under MATLAB/Simulink™
UserExecs
- Executables for the user models. One folder per executable.
UserSources
- Sources for the user models. All the source files pertaining to the model should reside in this directory. A default Makefile is provide when creating the user model under the SimConfig GUI. The user can modify these to suit the hierarchy of the source files. Nevertheless, the result of a make all command should always be to create the executable under the UserExecs/UserModelName/ folder.
Tests
- One sub folder per test. The sub folder name is the test name. It holds reference to the resources needed to run the test as well as one sub folder for each session run for the test.
Test Sessions
A sub folder under the test folder is created for each test run. This sub folder contains the results of the test run (logging data, log file) as well as the test results.
Script
- Contains the user test scripts (C,SWM,etc). One sub folder per test script. The sources and executable for the script reside in the sub folder specific to the test script.
Calibration
- Contains calibration files for the I/O boards used by SimWB. One calibration file per board instance. The file name is the BoardName.x where x is the board instance and BoardName is the name of the board as known under SimWB. I.e. AI64SS.1
SimWB HMI
How can I build custom HMI's in SimWB?
Can I add unicode characters, especially Japanese and Chinese characters to the Text Label in an HMI Display?
Yes, it is possible to embed Unicode characters in any HMI Display text label.
Troubleshooting
Why am I unable to view the debugger(kdbg) display when debugging a User or I/O task in SimWB?
In RedHawk 6.0 and later
- As part of IT security procedures, DisallowTCP is set to True in /etc/gdm/gdm.schemas which prevents kdbg from starting when the debug option is checked in SimWB. The option should be set to false as shown below. You will have to logout of X and log back in for the setting to take effect.
<schema> <key>security/DisallowTCP</key> <signature>b</signature> <default>false</default> </schema>
- Run the command xhost + in a terminal window running under the X server to disable access control to X server.
Performing the above steps should enable you to view the kdbg display when debugging a User or I/O task in SimWB.
Before RedHawk 6.0
- As part of IT security procedures, DisallowTCP=true is set in /etc/gdm/custom.conf which prevents kdbg from starting when the debug option is checked in SimWB. The option should be set to false, DisallowTCP=false. You will have to logout of X and log back in for the setting to take effect.
- Run the command xhost + in a terminal window running under the X server to disable access control to X server.
Performing the above steps should enable you to view the kdbg display when debugging a User or I/O task in SimWB.
How do I debug my source code in SimWB using the GUI?
Debugging source code under SimWB
SimWB provides the ability to debug models using KDbg. The following steps are needed to start the debugger from SimWB.
- First re-make the code with the –g flag. This is done by modifying the make file in the source code folder on the real-time host. This should be the default when generating the code from the SimWB MLToolkit.For example:
- Go to "/usr/local/ccursim/projects/RTW.Sources/modelname_ccurt" folder where "modelname" is the name of the model.
- Edit the "modelname.mk" file
- In the General User Options add the –g flag. Approximately line 153 in the MAKE file should now read OPTS = -g
- Use the commands "make –f modelname.mk clean" and "make –f modelname.mk" to remake the model.
- In the SimConfig GUI, go the test/session tab and select the test/session you want to run.
- Go to the Debug Options tab and make sure the Debug Selected Tasks checkbox is checked, the list of models in your test should appear in the list. Select the model you want to debug.
- Go back to the Run/Playback tab and click the Run button.
- The KDbg GUI will open and stop in the ccurrt_mainC.c file for this model. If the debugger stops in the schedutils.c task it is an indication that you need to remake the source with the –g file.
- If the debugger window does not open, look in the cfgsrv.log - under the cfgsrv tab in the message window. There will be a system message that indicates why SimWB could not open the debugger window in your X server. Refer to the step above on how to allow remote connection to your X server.
- Now you can place break points in the source code to debug the model. The model is called by the rt_OneStep() function.
Why do I receive license not available error even when I do have license?
SimWB uses the NightStar License Manager ('nslm') service to handle the licenses. The NSLM uses the unique system ID to validate the licenses. This system ID depends on MAC address among other things such as hard disk ID etc. When SimWB host (/usr/local/ccursim/bin/cfgsrv.sh) starts up it requests 'nslm' for license and proceeds if it acquires one. You may get license errors when
- There is no license. Renew license.
- There is no entry for localhost in /etc/hosts. It should always point to 127.0.0.1 and not the actual IP address of the machine (127.0.0.1 localhost).
- There is no entry for machine name in /etc/hosts. Suppose the IP address of the machine named 'ihawk' is 192.168.0.2, then /etc/hosts should contain '192.168.0.2 ihawk'.
- The machine is using another Ethernet card than it was configured. In other words, if the license id generated with say 'eth0' and if you are using 'eth1' with 'eth0' down, then licensing will fail. To workaround this, please assign a static IP address to 'eth0' and restart both network and nslm (service network restart; service nslm restart).