Difference between revisions of "SIMulation Workbench Architecture"
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[[File:simwb-architecture.png]] | [[File:simwb-architecture.png]] | ||
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+ | == Real-Time Host == | ||
+ | The real-time system hosts the memory resident real-time database (RTDB) and runs the data input and output tasks as well as the MATLAB RTW and user (Script) programs. | ||
+ | The simulation programs run in a continuous loop divided into sub cycles where each sub cycle is scheduled to execute exclusive of the others to avoid interference with one another and avoid the need to acquire locks on RTDB items. The four main sub cycles of executions are as follows: | ||
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+ | Hardware inputs: acquire hardware inputs, convert them to engineering units and store values in the RTDB. | ||
+ | Script program run. | ||
+ | Model program run. This sub cycle can itself be divided into multiple cycle when running multiple models whose execution is chained. | ||
+ | Hardware outputs: extract data values from the RTDB, convert from engineering units to raw value and generate hardware values. | ||
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+ | The main loop is dispatched by Concurrent Frequency Based Scheduler connected to a hardware timer on the RCIM® board. The sub cycles are executed sequentially where a sub cycle must wait for the preceding step to finish execution before it can run. | ||
+ | In addition to the software executing synchronously during the simulation loop, some processes run asynchronously to read inputs and write outputs to devices that are too slow to run at the speed of the simulation loop. Such devices include AFDX , ARINC 429, CAN I/O, 1553 I/O,etc. | ||
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+ | [[File:Soft-arch.png]] |
Revision as of 16:40, 18 November 2011
SIMulation Workbench can be configured either as monolithic system where both the real-time simulation applications and the data logger reside on the same host or as a distributed where the data logger run on a separate dedicated system. The system can thus be thought of as 2 logical systems. The simulation software runs on two logical systems interconnected via a TCP connection. The first system – the real-time host – hosts the real-time database and runs the MATLAB models while the second system serves as a data repository for test configuration data as well as logged data collected during a test run.
Real-Time Host
The real-time system hosts the memory resident real-time database (RTDB) and runs the data input and output tasks as well as the MATLAB RTW and user (Script) programs. The simulation programs run in a continuous loop divided into sub cycles where each sub cycle is scheduled to execute exclusive of the others to avoid interference with one another and avoid the need to acquire locks on RTDB items. The four main sub cycles of executions are as follows:
Hardware inputs: acquire hardware inputs, convert them to engineering units and store values in the RTDB. Script program run. Model program run. This sub cycle can itself be divided into multiple cycle when running multiple models whose execution is chained. Hardware outputs: extract data values from the RTDB, convert from engineering units to raw value and generate hardware values.
The main loop is dispatched by Concurrent Frequency Based Scheduler connected to a hardware timer on the RCIM® board. The sub cycles are executed sequentially where a sub cycle must wait for the preceding step to finish execution before it can run. In addition to the software executing synchronously during the simulation loop, some processes run asynchronously to read inputs and write outputs to devices that are too slow to run at the speed of the simulation loop. Such devices include AFDX , ARINC 429, CAN I/O, 1553 I/O,etc.